• image
  • image
  • image
  • image
  • image
  • image
  • image
  • image
  • image
  • image
Previous Next

PhotoniQ Architecture_smThe PhotoniQ models IQSP480 and IQSP580 consist of 32 input channels made up from four independent banks of 8 charge collection and data acquisition channels. Similarly, models IQSP482 and IQSP582 consist of 64 inputs allocated as 16 charge collection and data acquisition channels per bank.

 

Each bank is independently configured and triggered and generates eight parallel streams of digital data.

 

The dynamic range and data rate are dependent on the resolution/speed of the chosen model.

 

The intelligent trigger/acquisition module configures the triggering and acquisition parameters for each bank so any one of multiple triggering modes can be used to initiate the data acquisition process. On trigger, the PhotoniQ effectively takes a snapshot of all 32 or 64 channels, as the case may be.

 

Thirty-two parallel digital data channels are input to the Pipelined Parallel Processor (P3)—a dedicated high speed hardware processing unit that executes 32 parallel channels of computations on the digitised data streams from the front-end cells. For the 64 channel units, the two 32 channel data streams are multiplexed into the P3.

 

Each channel processor performs real-time data detection, buffering, and channel uniformity correction. The resulting data is sent through the Parallel Peripheral Interface (PPI) to the DSP where it is further processed then packetised and sent to the USB 2.0 output port.

 

Additional reserved DSP processing power is available to implement user defined filter, trigger, and data discrimination functions. This has the effect of reducing the downstream data rate to the PC which can increase throughput by orders of magnitude.

 

For more information on PhotoniQ's hardware architecture, see the following application note. PhotoniQ: Data Processing Architecture